{"id":80273,"date":"2024-10-17T18:42:42","date_gmt":"2024-10-17T18:42:42","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1754-1995\/"},"modified":"2024-10-24T19:42:59","modified_gmt":"2024-10-24T19:42:59","slug":"ieee-1754-1995","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1754-1995\/","title":{"rendered":"IEEE 1754 1995"},"content":{"rendered":"

New IEEE Standard – Inactive – Withdrawn. A 32-bit microprocessor architecture, available to a wide variety of manufacturers and users, is defined. The standard includes the definition of the instruction set, register model, data types, instruction op-codes, and coprocessor interface. You will receive an email from Customer Service with the URL needed to access this publication online.<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nTitle page <\/td>\n<\/tr>\n
3<\/td>\nIntroduction <\/td>\n<\/tr>\n
5<\/td>\nCommittee lists <\/td>\n<\/tr>\n
9<\/td>\nContents <\/td>\n<\/tr>\n
17<\/td>\n1. Overview <\/td>\n<\/tr>\n
21<\/td>\n2. Definitions, special word usage, abbreviations, and acronyms <\/td>\n<\/tr>\n
25<\/td>\n3. Architectural overview <\/td>\n<\/tr>\n
31<\/td>\n4. Data formats <\/td>\n<\/tr>\n
39<\/td>\n5. Registers <\/td>\n<\/tr>\n
57<\/td>\n6. Instructions <\/td>\n<\/tr>\n
71<\/td>\n7. Traps <\/td>\n<\/tr>\n
83<\/td>\nAnnex A\u2014Instruction definitions <\/td>\n<\/tr>\n
147<\/td>\nAnnex B\u2014ISP descriptions <\/td>\n<\/tr>\n
175<\/td>\nAnnex C\u2014IEEE 754 implementation requirements for IEEE 1754 <\/td>\n<\/tr>\n
179<\/td>\nAnnex D\u2014IEEE 1754 implementation dependencies <\/td>\n<\/tr>\n
193<\/td>\nAnnex E\u2014Opcodes and condition codes <\/td>\n<\/tr>\n
199<\/td>\nAnnex F\u2014IEEE 1754 Reference MMU architecture <\/td>\n<\/tr>\n
217<\/td>\nAnnex G\u2014Suggested ASI assignments <\/td>\n<\/tr>\n
225<\/td>\nAnnex H\u2014Example integer multiplication and division routines <\/td>\n<\/tr>\n
241<\/td>\nAnnex I\u2014Suggested assembly language syntax <\/td>\n<\/tr>\n
247<\/td>\nAnnex J\u2014Software considerations <\/td>\n<\/tr>\n
259<\/td>\nAnnex K\u2014Instruction set summary <\/td>\n<\/tr>\n
263<\/td>\nAnnex L\u2014Non-IEEE 1754 architectural extensions <\/td>\n<\/tr>\n
265<\/td>\nAnnex M\u2014Bibliography <\/td>\n<\/tr>\n
267<\/td>\nIndex <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for a 32-bit Microprocessor Architecture<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n1995<\/td>\n282<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":80274,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-80273","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/80273","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/80274"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=80273"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=80273"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=80273"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}