This part of IEC 62878 describes the test element group devices useful when measuring basic properties of device embedded substrates.<\/p>\n
This part of IEC 62878 is applicable to device embedded substrates fabricated by use of organic base material, which include for example active or passive devices, discrete components formed in the fabrication process of electronic wiring board, and sheet formed components.<\/p>\n
The IEC 62878 series neither applies to the re-distribution layer (RDL) nor to the electronic modules defined as an M-type business model in IEC 62421.<\/p>\n
| PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
|---|---|---|---|---|---|---|---|
| 4<\/td>\n | English CONTENTS <\/td>\n<\/tr>\n | ||||||
| 6<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
| 8<\/td>\n | INTRODUCTION <\/td>\n<\/tr>\n | ||||||
| 9<\/td>\n | 1 Scope 2 Normative references 3 Terms, definitions and abbreviations 3.1 Terms and definitions 3.2 Abbreviations 4 Test conditions and sample preparation 4.1 General 4.2 Test conditions 4.2.1 Classification of tests and evaluation <\/td>\n<\/tr>\n | ||||||
| 10<\/td>\n | 4.2.2 Measuring environment 4.2.3 Test methods 4.3 Test specimens and number of specimens 4.3.1 Specimen Tables Table 1 \u2013 Application and embedded device Table 2 \u2013 Measuring environment <\/td>\n<\/tr>\n | ||||||
| 11<\/td>\n | 4.3.2 Number of specimens 4.3.3 Test report 5 TEG 5.1 Preparation of the TEG <\/td>\n<\/tr>\n | ||||||
| 12<\/td>\n | Figures Figure 1 \u2013 Area array arrangement \u2013 TEG for conductor resistivity and via-to-via insulation <\/td>\n<\/tr>\n | ||||||
| 13<\/td>\n | Figure 2 \u2013 Area array arrangement \u2013 TEG for insulation measurement of resistance between conductors and insulation resistance between layers <\/td>\n<\/tr>\n | ||||||
| 14<\/td>\n | Figure 3 \u2013 Chip arrangement in a shot <\/td>\n<\/tr>\n | ||||||
| 15<\/td>\n | Figure 4 \u2013 Shot arrangement in a wafer <\/td>\n<\/tr>\n | ||||||
| 16<\/td>\n | Figure 5 \u2013 Pitch chip specification of peripheral terminal of 60(m TEG <\/td>\n<\/tr>\n | ||||||
| 17<\/td>\n | Figure 6 \u2013 Peripheral arrangement of TEG for complex tests <\/td>\n<\/tr>\n | ||||||
| 18<\/td>\n | Figure 7 \u2013 Chip arrangement in a shot Figure 8 \u2013 Shot arrangement in a wafer <\/td>\n<\/tr>\n | ||||||
| 19<\/td>\n | 5.2 Structures of TEG Figure 9 \u2013 Structure of test board and pad connection Figure 10 \u2013 Structure of a test board and via connection <\/td>\n<\/tr>\n | ||||||
| 20<\/td>\n | 5.3 Test pattern guide 5.3.1 Test items Table 3 \u2013 Test items <\/td>\n<\/tr>\n | ||||||
| 21<\/td>\n | 5.3.2 Area array arrangement of TEG for an active device Figure 11 \u2013 Area array arrangement <\/td>\n<\/tr>\n | ||||||
| 22<\/td>\n | 5.3.3 Peripheral arrangement of TEG Table 4 \u2013 Terminal dimensions <\/td>\n<\/tr>\n | ||||||
| 23<\/td>\n | Figure 12 \u2013 Peripheral arrangement of TEG Table 5 \u2013 Detailed dimensions of the peripheral arrangement of TEG <\/td>\n<\/tr>\n | ||||||
| 24<\/td>\n | Figure 13 \u2013 Example of pad arrangement of peripherals Table 6 \u2013 Detailed dimensions of the peripheral arrangement of pad connections <\/td>\n<\/tr>\n | ||||||
| 25<\/td>\n | 5.3.4 TEG size for active devices Figure 14 \u2013 TEG size of active device <\/td>\n<\/tr>\n | ||||||
| 26<\/td>\n | 5.3.5 TEG for passive devices 5.3.6 Complex test pattern for the area arrangement, TEG-A Figure 15 \u2013 TEG for passive device Table 7 \u2013 Dimension of passive device TEG <\/td>\n<\/tr>\n | ||||||
| 27<\/td>\n | Figure 16 \u2013 Test pattern for conduction and insulation resistance between vias (seen from L6) Table 8 \u2013 Dimensions of the area array arrangement of TEG-A <\/td>\n<\/tr>\n | ||||||
| 28<\/td>\n | Figure 17 \u2013 Complex test patterns for conduction and via-to-via insulation <\/td>\n<\/tr>\n | ||||||
| 29<\/td>\n | 5.3.7 Complex pattern for area arrangement of TEG-B Figure 18 \u2013 Test patterns for insulation between conductor and between layers in an area array arrangement Table 9 \u2013 Dimensions of TEG-B for the area array arrangement <\/td>\n<\/tr>\n | ||||||
| 30<\/td>\n | Figure 19 \u2013 Complex test patterns for L1 to L6 for insulation between conductors and layers <\/td>\n<\/tr>\n | ||||||
| 31<\/td>\n | 5.3.8 Complex test pattern for peripheral arrangement Figure 20 \u2013 L1 to L6 complex test patterns for the peripheral arrangement <\/td>\n<\/tr>\n | ||||||
| 32<\/td>\n | 5.3.9 Complex test pattern for passive components Figure 21 \u2013 Conduction test patterns for L1 to L6 of passive components <\/td>\n<\/tr>\n | ||||||
| 33<\/td>\n | Figure 22 \u2013 Insulation test patterns between terminals for L1 to L6 of passive components <\/td>\n<\/tr>\n | ||||||
| 34<\/td>\n | Figure 23 \u2013 Interlayer insulation test patterns of L1 to L6 of passive components <\/td>\n<\/tr>\n | ||||||
| 35<\/td>\n | 5.3.10 Guide of measurement terminals of a complex test pattern for an active device Figure 24 \u2013 Terminal arrangement (1) for measurement and evaluation using complex pattern for an active device <\/td>\n<\/tr>\n | ||||||
| 36<\/td>\n | 5.3.11 Terminal arrangement using complex patterns Figure 25 \u2013 Terminal arrangement (2) for measurement and evaluation using complex pattern for an active device <\/td>\n<\/tr>\n | ||||||
| 37<\/td>\n | Figure 26 \u2013 Terminal arrangement for measurement and evaluation using complex pattern for passive device Figure 27 \u2013 Terminal arrangement for measurement and evaluation using complex pattern for device embedded substrate <\/td>\n<\/tr>\n | ||||||
| 38<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Device embedded substrate – Guidelines. Test element groups (TEG)<\/b><\/p>\n |