{"id":400163,"date":"2024-10-20T04:47:46","date_gmt":"2024-10-20T04:47:46","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-2977-2021\/"},"modified":"2024-10-26T08:35:48","modified_gmt":"2024-10-26T08:35:48","slug":"ieee-2977-2021","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-2977-2021\/","title":{"rendered":"IEEE 2977-2021"},"content":{"rendered":"

New IEEE Standard – Active. This standard adopts MIPI Alliance–MIPI A-PHY Specification Version 1.0 as an IEEE Standard. The adopted standard provides an asymmetric data link in a point-to-point or daisy-chain topology, with high-speed unidirectional data, embedded bidirectional control data and optional power delivery over a single cable. In this way, it reduces wiring, cost and weight, as high-speed data, control data and optional power share the same physical wiring. For integration with existing network backbones, it complements Ethernet, Controller Area Network (CAN), FlexRay, and other interfaces.<\/p>\n

PDF Catalog<\/h4>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nFront Cover <\/td>\n<\/tr>\n
2<\/td>\nTitle page <\/td>\n<\/tr>\n
4<\/td>\nNotice and Disclaimer of Liability Concerning the Use of IEEE Standards Documents <\/td>\n<\/tr>\n
8<\/td>\nParticipants <\/td>\n<\/tr>\n
9<\/td>\nIntroduction <\/td>\n<\/tr>\n
10<\/td>\nSpecification for A-PHY
Contents <\/td>\n<\/tr>\n
16<\/td>\nFigures <\/td>\n<\/tr>\n
20<\/td>\nTables <\/td>\n<\/tr>\n
24<\/td>\nRelease History <\/td>\n<\/tr>\n
26<\/td>\n1 Introduction
1.1 Scope
1.1.1 In Scope
1.1.2 Out of Scope
1.2 Purpose <\/td>\n<\/tr>\n
27<\/td>\n2.1 Use of Special Terms
2.2 Definitions <\/td>\n<\/tr>\n
28<\/td>\n2.3 Abbreviations <\/td>\n<\/tr>\n
29<\/td>\n2.4 Acronyms <\/td>\n<\/tr>\n
31<\/td>\n3 References <\/td>\n<\/tr>\n
33<\/td>\n4 Overview <\/td>\n<\/tr>\n
35<\/td>\n5 Architecture
5.1 High Level Structure <\/td>\n<\/tr>\n
36<\/td>\n5.2 Profiles <\/td>\n<\/tr>\n
37<\/td>\n5.3 Gears <\/td>\n<\/tr>\n
38<\/td>\n5.4 Safety <\/td>\n<\/tr>\n
40<\/td>\n6 Interconnect
6.1 Lane Configuration
6.2 Cable Topology <\/td>\n<\/tr>\n
41<\/td>\n6.3 Boundary Conditions
6.4 S-Parameter Specifications
6.5 Characterization Conditions <\/td>\n<\/tr>\n
42<\/td>\n6.6 Interconnect Specifications <\/td>\n<\/tr>\n
43<\/td>\n6.6.1 Total Interconnect
6.6.2 Cable TLIS (Transmission Line Interconnect Structure)
6.6.2.1 Characteristic Impedance
6.6.2.2 Insertion Loss <\/td>\n<\/tr>\n
44<\/td>\n6.6.2.3 Return Loss <\/td>\n<\/tr>\n
45<\/td>\n6.6.2.4 Coupling Attenuation <\/td>\n<\/tr>\n
47<\/td>\n6.6.2.5 Alien Cable Bundle Crosstalk <\/td>\n<\/tr>\n
48<\/td>\n6.6.3 ENIS (End Node Interconnect Structure)
6.6.3.1 Characteristic Impedance <\/td>\n<\/tr>\n
49<\/td>\n6.6.3.2 Insertion Loss <\/td>\n<\/tr>\n
50<\/td>\n6.6.3.3 Return Loss <\/td>\n<\/tr>\n
51<\/td>\n6.6.3.4 Mode Conversion
6.6.3.5 Receiver Alien Near End Crosstalk <\/td>\n<\/tr>\n
52<\/td>\n6.6.4 PCB TLIS (Transmission Line Interconnect Structure) (Informative) <\/td>\n<\/tr>\n
53<\/td>\n6.6.4.1 Characteristic Impedance
6.6.4.2 Insertion Loss
6.6.4.3 Return Loss
6.6.5 Power Distribution
6.6.5.1 DC Requirements <\/td>\n<\/tr>\n
54<\/td>\n6.6.5.2 AC Requirements <\/td>\n<\/tr>\n
55<\/td>\n6.6.5.3 Power Over Coax
6.6.5.4 Power Over Differential Line <\/td>\n<\/tr>\n
56<\/td>\n6.6.6 Ground Voltage Offset <\/td>\n<\/tr>\n
57<\/td>\n7 EMC Environmental Conditions
7.1 RF Ingress
7.2 Bulk Current Injection (BCI) <\/td>\n<\/tr>\n
58<\/td>\n7.3 Fast Transient
7.4 Alien Cable Bundle Max PSD Level <\/td>\n<\/tr>\n
59<\/td>\n7.5 Car Noise (PSD) <\/td>\n<\/tr>\n
60<\/td>\n8 PHY Layer
8.1 Architecture
8.1.1 High Level Structure
8.1.2 Port Specification Generalization <\/td>\n<\/tr>\n
61<\/td>\n8.1.3 Master\/Slave Clocking Schemes
8.1.4 PHY Layer Implementation Guidelines
8.1.4.1 A-PHY P1 G1\/G2 Architecture <\/td>\n<\/tr>\n
62<\/td>\n8.1.4.2 A-PHY P2 G1\/G2 Architecture <\/td>\n<\/tr>\n
63<\/td>\n8.1.4.3 A-PHY G3\u2013G5 Architecture <\/td>\n<\/tr>\n
65<\/td>\n8.1.5 PHY-Related A-Packet Fields
8.2 RTS <\/td>\n<\/tr>\n
70<\/td>\n8.2.1 PAM-X Payload Data Modulation Assignment by Source <\/td>\n<\/tr>\n
71<\/td>\n8.2.2 Active Message Counter Window
Informative Implementation Note
8.2.3 Retransmission Request \/ Ack Types <\/td>\n<\/tr>\n
72<\/td>\nInformative Note
8.2.3.1 Retransmission Request Triggering by the Receiver <\/td>\n<\/tr>\n
73<\/td>\nExample: Recurrent, Unsatisfied Retransmission, Request Generation (Informative)
8.2.3.2 Retransmission Request Handling at TX RTS
8.2.3.3 Format of Single\/Gap Retransmission Request Sent Over Downlink <\/td>\n<\/tr>\n
75<\/td>\n8.2.4 Time Bounded RTS <\/td>\n<\/tr>\n
76<\/td>\n8.2.5 A-Packet \u2013 PHY Related Header\/Tail Modifications
8.2.5.1 Tx Delay
8.2.5.2 Message Counter and Original Indication Bit
8.2.5.3 Header CRC (CRC-8) <\/td>\n<\/tr>\n
78<\/td>\n8.2.5.4 A-Packet Tail CRC (CRC-32) <\/td>\n<\/tr>\n
79<\/td>\n8.2.6 Fully Paced A-Packet Stream from TX Data Link Layer to TX RTS
8.2.6.1 Max Net Link Rate for 8B\/10B PCS
8.2.6.2 Max Net Link Rate for PAM-X PCS
8.2.6.3 8B\/10B PCS Fully Paced, A-Packets Stream from Link to TX RTS <\/td>\n<\/tr>\n
80<\/td>\n8.2.6.4 PAM-X PCS Fully Paced, A-Packets Stream from Link to TX RTS <\/td>\n<\/tr>\n
81<\/td>\nPAM-X Pacing Implementation Example (Informative)
8.2.7 Retransmitted A-Packets Scheduling Priority at TX RTS
8.2.8 RTS Bypass <\/td>\n<\/tr>\n
83<\/td>\n8.3 Physical Coding Sub-Layer (PCS)
8.3.1 PAM-X PCS <\/td>\n<\/tr>\n
84<\/td>\n8.3.1.1 PAM16 Sub-Constellation Bit to Symbol mapping <\/td>\n<\/tr>\n
86<\/td>\n8.3.1.2 Symbol and Token Rate\/Period <\/td>\n<\/tr>\n
88<\/td>\n8.3.1.3 A-Packet to Token Conversion <\/td>\n<\/tr>\n
90<\/td>\n8.3.1.4 Downlink Scrambler <\/td>\n<\/tr>\n
91<\/td>\n8.3.1.5 Downlink Training Mode <\/td>\n<\/tr>\n
93<\/td>\n8.3.1.5.1 Mode Transition from Training to Idle <\/td>\n<\/tr>\n
94<\/td>\n8.3.1.6 Downlink Idle Mode
8.3.1.7 Downlink Normal Mode <\/td>\n<\/tr>\n
96<\/td>\n8.3.1.8 Downlink JITC Re-Training <\/td>\n<\/tr>\n
97<\/td>\n8.3.2 8B\/10B PCS <\/td>\n<\/tr>\n
98<\/td>\n8.3.2.1 10b Symbols to NRZ Mapping
8.3.2.2 8B\/10B Encoding
8.3.2.3 Uplink Scrambler <\/td>\n<\/tr>\n
99<\/td>\n8.3.2.4 Downlink Scrambler
8.3.2.5 Byte Stream Controller
8.3.2.5.1 Data Bytes
8.3.2.5.2 Control Byte
8.3.2.5.3 Startup Control Sequence <\/td>\n<\/tr>\n
100<\/td>\n8.3.2.5.4 Normal Control Sequence
8.3.2.6 Training Mode <\/td>\n<\/tr>\n
101<\/td>\n8.3.2.7 Idle Mode <\/td>\n<\/tr>\n
102<\/td>\n8.3.2.8 Normal Mode
8.3.2.8.1 Re-Train Request <\/td>\n<\/tr>\n
103<\/td>\n8.3.2.8.2 sCMax Request
8.3.2.8.3 Single Retransmission Request
8.3.2.8.4 Retransmission Gap Request <\/td>\n<\/tr>\n
104<\/td>\n8.3.2.8.5 Ack Indication
8.3.2.8.6 Data Packet <\/td>\n<\/tr>\n
105<\/td>\n8.3.3 Startup Procedure <\/td>\n<\/tr>\n
106<\/td>\n8.3.3.1 \u201cMission Mode\u201d Startup Procedure <\/td>\n<\/tr>\n
108<\/td>\n8.3.3.2 Unidirectional Startup Procedure <\/td>\n<\/tr>\n
111<\/td>\n9 PMD Electrical Specification
9.1 TX Electrical Specification
9.1.1 Test Mode Pattern Generator (TMPG) <\/td>\n<\/tr>\n
112<\/td>\n9.1.1.1 LFSR Usage Example <\/td>\n<\/tr>\n
114<\/td>\n9.1.2 Test Modes
9.1.2.1 TM1: Test Mode 1: Transmit PSD
9.1.2.2 TM2: Test Mode 2: Droop <\/td>\n<\/tr>\n
115<\/td>\n9.1.2.3 TM3: Test Mode 3: Transmit Jitter
9.1.2.4 TM4: Test Mode 4: Transmit Linearity
9.1.2.5 TM5: Test Mode 5: In Silent State
9.1.2.6 TM6: Test Mode 6: Unidirectional Startup
9.1.3 Transmitter Power Spectral Density Mask
9.1.3.1 Requirement <\/td>\n<\/tr>\n
116<\/td>\n9.1.3.1.1 NRZ PMD PSD Limits <\/td>\n<\/tr>\n
117<\/td>\n9.1.3.1.2 Uplink PMD PSD Limits <\/td>\n<\/tr>\n
118<\/td>\n9.1.3.1.3 PAM-X PMD PSD Limits <\/td>\n<\/tr>\n
119<\/td>\n9.1.3.2 Processing Procedure
9.1.3.2.1 Matlab Example Code (Informative) <\/td>\n<\/tr>\n
123<\/td>\n9.1.4 Transmitter Maximum Output Droop
9.1.4.1 Requirement
9.1.4.2 Processing Procedure
9.1.5 Transmitter Timing Jitter
9.1.5.1 Requirement
9.1.5.2 Processing Procedure <\/td>\n<\/tr>\n
124<\/td>\n9.1.6 Transmitter Symbol Rate Accuracy
9.1.7 NRZ Downlink Transmitter Eye Opening
9.1.7.1 Requirement
9.1.7.2 Processing Procedure <\/td>\n<\/tr>\n
125<\/td>\n9.1.7.3 NRZ Jitter (Informative) <\/td>\n<\/tr>\n
126<\/td>\n9.1.8 PAM-X Transmitter Linearity
9.1.8.1 Requirement
9.1.8.2 Processing Procedure <\/td>\n<\/tr>\n
127<\/td>\n9.1.8.2.1 Matlab Example Code (Informative) <\/td>\n<\/tr>\n
129<\/td>\n9.2 RX Electrical Specification
9.2.1 Profile 1 Receiver Bit Error Rate
9.2.2 Profile 2 Downlink Receiver Pre-RTS Packet Error Rate
9.2.3 Profile 2 Uplink Receiver Bit Error Rate
9.2.4 Receiver Symbol Rate Frequency Tolerance
9.2.5 Receiver Test Modes
9.2.5.1 RTM6: Receiver Test Mode 6: Unidirectional Startup <\/td>\n<\/tr>\n
131<\/td>\n10 Modes of Operation
10.1 Non-Active Mode
10.2 Active Mode
10.3 Operation Mode State Machine <\/td>\n<\/tr>\n
132<\/td>\n10.3.1 General Operation
10.3.2 States <\/td>\n<\/tr>\n
133<\/td>\n10.3.2.1 Power-Up State
10.3.2.2 Start-Up State
10.3.2.3 Normal State
10.3.2.4 Sleep State <\/td>\n<\/tr>\n
134<\/td>\n10.3.3 Transitions
10.3.3.1 Power-Off Transition
10.3.3.2 Reset Transition
10.3.3.3 Ready Transition
10.3.3.4 Stop Transition <\/td>\n<\/tr>\n
135<\/td>\n10.3.3.5 Link Establish Transition
10.3.3.6 Link Down Transition
10.3.3.7 Sleep Transition <\/td>\n<\/tr>\n
136<\/td>\n10.3.3.8 Wakeup Transition
10.3.4 Test Mode <\/td>\n<\/tr>\n
137<\/td>\n10.4 FSM Parameters <\/td>\n<\/tr>\n
138<\/td>\n10.5 Wake-Up Protocol
10.5.1 General
10.5.1.1 System Architecture (Informative) <\/td>\n<\/tr>\n
141<\/td>\n10.5.2 Wake-Up Pattern (WUP) Signal
10.5.2.1 PRBS9 Pattern
10.5.2.2 WUP Amplitude <\/td>\n<\/tr>\n
142<\/td>\n10.5.2.3 WUP Bit Rate
10.5.2.4 WUP Duration
10.5.2.5 WUP Generation
10.5.2.6 WUP Detection
10.5.3 WUP Handshake Procedure <\/td>\n<\/tr>\n
143<\/td>\n10.5.4 WUP Parameters <\/td>\n<\/tr>\n
144<\/td>\n11 Data Link Layer
11.1 Architecture Overview <\/td>\n<\/tr>\n
146<\/td>\n11.2 A-Packet Format <\/td>\n<\/tr>\n
147<\/td>\n11.2.1 A-Packet Header (A-Header) Fields <\/td>\n<\/tr>\n
148<\/td>\n11.2.1.1 Adaptation Descriptor Field
11.2.1.1.1 Adaptation Type Sub-Field
11.2.1.2 Service Descriptor Field
11.2.1.2.1 PHY1 Sub-Field
11.2.1.2.2 Prio Sub-Field <\/td>\n<\/tr>\n
149<\/td>\n11.2.1.2.3 QoS Sub-Field
11.2.1.2.4 BAD Sub-Field <\/td>\n<\/tr>\n
151<\/td>\n11.2.1.3 Placement Descriptor Field
11.2.1.3.1 ALEI (Adaptation Layer Extended Info) Sub-Field
11.2.1.3.2 OB (Odd-Bytes) Sub-Field
11.2.1.3.3 Order Sub-Field
11.2.1.4 PHY2 Field
11.2.1.5 Target Address Field <\/td>\n<\/tr>\n
153<\/td>\n11.2.1.6 PHY3 Field
11.2.1.7 Payload Length Field
11.2.1.8 PHY Header CRC Field
11.2.2 A-Packet Payload (A-Payload)
11.2.3 A-Packet Tail (A-Tail) (CRC-32 Field) <\/td>\n<\/tr>\n
154<\/td>\n11.3 Link Service
11.3.1 BIST A-Packet
11.3.1.1 BIST Modes
11.3.1.2 BIST Payload Patterns
11.3.1.3 BIST Rate <\/td>\n<\/tr>\n
155<\/td>\n11.3.1.4 BIST Burst
11.3.2 Keep-Alive
11.3.3 Remote Sleep Command <\/td>\n<\/tr>\n
156<\/td>\n11.4 Local Functions
11.4.1 Local Table (LOC_TBL) Recommendations (Informative) <\/td>\n<\/tr>\n
158<\/td>\n11.5 Multi-Port Functions <\/td>\n<\/tr>\n
159<\/td>\n11.5.1 Multi-Port Routing Function
11.5.1.1 Packet Duplication Stage
11.5.1.2 Packet Forwarding Stage <\/td>\n<\/tr>\n
160<\/td>\n11.5.1.3 Routing Table (ROUT_TBL) Recommendations (Informative)
11.5.1.4 Duplication Table (DUP_TBL) Recommendations (Informative) <\/td>\n<\/tr>\n
162<\/td>\n11.6 Network Functions
11.6.1 Scheduling and Priorities
11.6.2 Clock Forwarding Service
11.6.2.1 CFS A-Packet Format <\/td>\n<\/tr>\n
163<\/td>\n11.6.2.1.1 Frequency Offset (FreqOffset) Field
11.6.2.1.2 Adaptation Layer Type (AL_Type) Field
11.6.2.1.3 Measurement Field
11.6.2.1.4 Accumulated Delay (ACC_DELAY) Field
11.7 APPI Signal Interface <\/td>\n<\/tr>\n
164<\/td>\n11.7.1 Signals Description
11.7.1.1 APPI Signals <\/td>\n<\/tr>\n
165<\/td>\n11.7.2 APPI Clock <\/td>\n<\/tr>\n
166<\/td>\n11.7.3 APPI A-Packet Mapping
11.7.4 APPI Timing Diagrams <\/td>\n<\/tr>\n
169<\/td>\n12 A-PHY Control and Management Database (ACMD) and Protocol (ACMP) <\/td>\n<\/tr>\n
170<\/td>\n12.1 Control and Management System Architecture (Informative) <\/td>\n<\/tr>\n
171<\/td>\n12.2 ACMD
12.2.1 Register Base Address Alignment
12.2.2 Register Data Byte Order <\/td>\n<\/tr>\n
172<\/td>\n12.2.3 Register Space <\/td>\n<\/tr>\n
173<\/td>\n12.2.4 Register List <\/td>\n<\/tr>\n
175<\/td>\n12.2.5 Detailed Register Description
12.2.5.1 ACMD Programming <\/td>\n<\/tr>\n
179<\/td>\n12.2.5.2 Port Programming <\/td>\n<\/tr>\n
185<\/td>\n12.3 ACMP <\/td>\n<\/tr>\n
186<\/td>\n12.3.1 ACMP Message Format
12.3.1.1 ACMP Message Header Part <\/td>\n<\/tr>\n
187<\/td>\n12.3.1.1.1 Header CRC (HCRC) Field
12.3.1.2 ACMP Message Payload Part <\/td>\n<\/tr>\n
188<\/td>\n12.3.1.2.1 Payload CRC (PCRC) <\/td>\n<\/tr>\n
189<\/td>\n12.3.1.3 ACMP Message Mapping to I2C <\/td>\n<\/tr>\n
190<\/td>\n12.3.2 ACMP Message Receiver Rules and Responsibilities
12.3.2.1 ACMP Header CRC (HCRC) Errors
12.3.2.2 ACMP Payload CRC (PCRC) Errors
12.3.2.3 Message Counter (MC)
12.3.2.4 Keep-Alive
12.3.2.5 Message Format Setting
12.3.2.6 Virtual Base Address Maintenance
12.3.2.7 Accessing Register Data
12.3.3 ACMP Interrupts <\/td>\n<\/tr>\n
191<\/td>\n12.3.3.1 ACMPI in I2C
12.3.3.2 ACMPI in I3C <\/td>\n<\/tr>\n
192<\/td>\nAnnex A PMD Simplified Implementation Examples (Informative) <\/td>\n<\/tr>\n
196<\/td>\nParticipants <\/td>\n<\/tr>\n
198<\/td>\nAnnex B (informative) Exerpt from Specification for M-PHY\u00ae <\/td>\n<\/tr>\n
205<\/td>\nBack Cover <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for Adoption of MIPI Alliance Specification for A-PHY Interface (A-PHY) Version 1.0<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2021<\/td>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":400164,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-400163","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/400163","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/400164"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=400163"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=400163"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=400163"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}