{"id":361660,"date":"2024-10-20T01:37:00","date_gmt":"2024-10-20T01:37:00","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-iso-20794-72020\/"},"modified":"2024-10-26T02:30:36","modified_gmt":"2024-10-26T02:30:36","slug":"bs-iso-20794-72020","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-iso-20794-72020\/","title":{"rendered":"BS ISO 20794-7:2020"},"content":{"rendered":"
This document specifies the conformance test plans for the CXPI data link layer and the CXPI physical layer. It also specifies the conformance test plan for error detection.<\/p>\n
Additionally, this document describes the concept of conformance test plan operation.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
---|---|---|---|---|---|---|---|
2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | Foreword <\/td>\n<\/tr>\n | ||||||
9<\/td>\n | Introduction <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | 1 Scope 2 Normative references 3 Terms and definitions 4 Symbols and abbreviated terms 4.1 Symbols <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | 4.2 Abbreviated terms <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | 5 Conventions 6 General test specification considerations 6.1 General <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | 6.2 Test conditions 6.3 IUT requirements 6.4 CTC definition <\/td>\n<\/tr>\n | ||||||
15<\/td>\n | 6.5 Test system set-up <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | 6.6 Configuration of test system and IUT 6.6.1 General <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | 6.6.2 IUT-specific set-up parameters <\/td>\n<\/tr>\n | ||||||
18<\/td>\n | 6.6.3 Default configurations 6.6.4 L_ErrDet1 configurations 6.6.5 L_ErrDet2 configurations 6.6.6 L_Arbit configurations 6.6.7 L_Unknown configurations 6.7 SUT initialisation <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | 6.8 Additional test system set-up capabilities 6.8.1 CXPI network data generator <\/td>\n<\/tr>\n | ||||||
21<\/td>\n | 6.8.2 TXD data generator <\/td>\n<\/tr>\n | ||||||
23<\/td>\n | 6.8.3 TXPWM data generator <\/td>\n<\/tr>\n | ||||||
24<\/td>\n | 6.8.4 RXPWM data generator <\/td>\n<\/tr>\n | ||||||
26<\/td>\n | 6.8.5 Other requirements 7 Data link layer conformance test plan 7.1 General 7.2 CTP \u2013 Timing parameters 7.2.1 2.CTC_1.1 \u2013 IBS length <\/td>\n<\/tr>\n | ||||||
27<\/td>\n | 7.2.2 2.CTC_1.2 \u2013 IFS length <\/td>\n<\/tr>\n | ||||||
28<\/td>\n | 7.2.3 2.CTC_1.3 \u2013 Frame reception starting condition 1 without the error bit 7.2.4 2.CTC_1.4 \u2013 Frame reception starting condition 1 with the error bit <\/td>\n<\/tr>\n | ||||||
29<\/td>\n | 7.2.5 2.CTC_1.5 \u2013 Frame reception starting condition 2 without the error bit <\/td>\n<\/tr>\n | ||||||
30<\/td>\n | 7.2.6 2.CTC_1.6 \u2013 Frame reception starting condition 2 with the error bit 7.2.7 2.CTC_1.7 \u2013 Frame reception starting condition 3 <\/td>\n<\/tr>\n | ||||||
31<\/td>\n | 7.2.8 2.CTC_1.8 \u2013 Maximum length of the frame <\/td>\n<\/tr>\n | ||||||
32<\/td>\n | 7.3 CTP \u2013 Frame transmission\/reception 7.3.1 2.CTC_2.1 \u2013 Response to L_PID field <\/td>\n<\/tr>\n | ||||||
33<\/td>\n | 7.3.2 2.CTC_2.2 \u2013 L_PID field transmission 7.3.3 2.CTC_2.3 \u2013 L_PTYPE field transmission <\/td>\n<\/tr>\n | ||||||
34<\/td>\n | 7.3.4 2.CTC_2.4 \u2013 L_PTYPE field response function <\/td>\n<\/tr>\n | ||||||
35<\/td>\n | 7.3.5 2.CTC_2.5 \u2013 L_FI_DLC \u2260 11112 and frame data verification 1 <\/td>\n<\/tr>\n | ||||||
36<\/td>\n | 7.3.6 2.CTC_2.6 \u2013 L_FI_DLC \u2260 11112 and frame data verification 2 if DLC is 11012 or 11102 (Ftype = NormalCom) <\/td>\n<\/tr>\n | ||||||
37<\/td>\n | 7.3.7 2.CTC_2.7 \u2013 L_FI_DLC = 11112\/L_FI_DLCext \u2265 0 and frame data verification <\/td>\n<\/tr>\n | ||||||
38<\/td>\n | 7.3.8 2.CTC_2.8 \u2013 Given CRC of frame with L_FI_DLC \u2260 11112 <\/td>\n<\/tr>\n | ||||||
39<\/td>\n | 7.3.9 2.CTC_2.9 \u2013 Given CRC of frame with L_FI_DLC = 11112\/L_FI_DLCext \u2265 0 <\/td>\n<\/tr>\n | ||||||
40<\/td>\n | 7.3.10 2.CTC_2.10 \u2013 Frame transmission completion 7.3.11 2.CTC_2.11 \u2013 Frame reception completion <\/td>\n<\/tr>\n | ||||||
41<\/td>\n | 7.4 CTP \u2013 Network access 7.4.1 2.CTC_3.1 \u2013 Arbitration function 1 (arbitration by using carrier sense) <\/td>\n<\/tr>\n | ||||||
42<\/td>\n | 7.4.2 2.CTC_3.2 \u2013 Arbitration function 2 (IUT loses arbitration and transitions into receiving state) <\/td>\n<\/tr>\n | ||||||
43<\/td>\n | 7.5 CTP \u2013 Error detection 7.5.1 2.CTC_4.1 \u2013 Byte error <\/td>\n<\/tr>\n | ||||||
45<\/td>\n | 7.5.2 2.CTC_4.2 \u2013 CRC error <\/td>\n<\/tr>\n | ||||||
46<\/td>\n | 7.5.3 2.CTC_4.3 \u2013 Parity error of the L_PID field without the error bit <\/td>\n<\/tr>\n | ||||||
47<\/td>\n | 7.5.4 2.CTC_4.4 \u2013 Parity error of the L_PID field with the error bit 7.5.5 2.CTC_4.5 \u2013 Parity error of the L_PTYPE field without the error bit <\/td>\n<\/tr>\n | ||||||
48<\/td>\n | 7.5.6 2.CTC_4.6 \u2013 Parity error of the L_PTYPE field with the error bit <\/td>\n<\/tr>\n | ||||||
49<\/td>\n | 7.5.7 2.CTC_4.7 \u2013 Data length code error with L_FI_DLC \u2260 11112 <\/td>\n<\/tr>\n | ||||||
50<\/td>\n | 7.5.8 2.CTC_4.8 \u2013 Data length error with L_FI_DLC = 11112\/L_FI_DLCext \u2265 0 <\/td>\n<\/tr>\n | ||||||
51<\/td>\n | 7.5.9 2.CTC_4.9 \u2013 Data length code error L_FI_DLC \u2260 11112 and if DLC is 11012 or 11102 (Ftype = DiagNodeCfg) <\/td>\n<\/tr>\n | ||||||
52<\/td>\n | 7.5.10 2.CTC_4.10 \u2013 Data length code error L_FI_DLC = 11112\/L_FI_DLCext \u2264 12 (Ftype = DiagNodeCfg) <\/td>\n<\/tr>\n | ||||||
53<\/td>\n | 7.5.11 2.CTC_4.11 \u2013 Framing error in receiving node <\/td>\n<\/tr>\n | ||||||
54<\/td>\n | 7.5.12 2.CTC_4.12 \u2013 Framing error in transmitting node 7.5.13 2.CTC_4.13 \u2013 Ignore error (no support of L_FI_DLC = 11112) <\/td>\n<\/tr>\n | ||||||
55<\/td>\n | 8 Physical layer conformance test plan (PMA \u2013 PS separate type) 8.1 CTP \u2013 Operational conditions and calibration 8.1.1 Initial configuration <\/td>\n<\/tr>\n | ||||||
56<\/td>\n | 8.1.2 1.CTC_1.1 \u2013 Clock transmission 1 <\/td>\n<\/tr>\n | ||||||
57<\/td>\n | 8.1.3 1.CTC_1.2 \u2013 Clock transmission 2 <\/td>\n<\/tr>\n | ||||||
59<\/td>\n | 8.1.4 1.CTC_1.3 \u2013 Clock transmission 3 <\/td>\n<\/tr>\n | ||||||
61<\/td>\n | 8.1.5 1.CTC_1.4 \u2013 Detection of clock existence <\/td>\n<\/tr>\n | ||||||
62<\/td>\n | 8.1.6 1.CTC_1.5 \u2013 Arbitration function (stop transmission by arbitration) <\/td>\n<\/tr>\n | ||||||
64<\/td>\n | 8.1.7 1.CTC_1.6 \u2013 Operating voltage range <\/td>\n<\/tr>\n | ||||||
65<\/td>\n | 8.1.8 1.CTC_1.7 \u2013 Bit synchronisation <\/td>\n<\/tr>\n | ||||||
67<\/td>\n | 8.2 CTP \u2013 Wake-up pulse 8.2.1 General 8.2.2 1.CTC_2.1 \u2013 Wake-up pulse reception 1, IUT as master node <\/td>\n<\/tr>\n | ||||||
69<\/td>\n | 8.2.3 1.CTC_2.2 \u2013 Wake-up pulse reception 2, IUT as slave node <\/td>\n<\/tr>\n | ||||||
71<\/td>\n | 8.2.4 1.CTC_2.3 \u2013 Wake-up pulse transmission <\/td>\n<\/tr>\n | ||||||
73<\/td>\n | 8.3 CTP \u2013 Voltage and duty cycle thresholds 8.3.1 General 8.3.2 Voltage threshold test set-up 8.3.3 1.CTC_3.1 \u2013 Voltage threshold test 1 <\/td>\n<\/tr>\n | ||||||
74<\/td>\n | 8.3.4 1.CTC_3.2 \u2013 Voltage threshold (VDom_TS up) test 2 <\/td>\n<\/tr>\n | ||||||
76<\/td>\n | 8.3.5 1.CTC_3.2 \u2013 Voltage threshold test 2 <\/td>\n<\/tr>\n | ||||||
77<\/td>\n | 8.3.6 1.CTC_3.3 \u2013 Duty cycle threshold test 1 <\/td>\n<\/tr>\n | ||||||
78<\/td>\n | 8.3.7 1.CTC_3.4 \u2013 Duty cycle threshold test 2 <\/td>\n<\/tr>\n | ||||||
79<\/td>\n | 8.4 CTP \u2013 Network state current characteristics 8.4.1 1.CTC_4.1 \u2013 Drive current test <\/td>\n<\/tr>\n | ||||||
81<\/td>\n | 8.4.2 1.CTC_4.2 \u2013 Input leakage test <\/td>\n<\/tr>\n | ||||||
82<\/td>\n | 8.4.3 1.CTC_4.3 \u2013 Reverse leakage current test <\/td>\n<\/tr>\n | ||||||
83<\/td>\n | 8.5 CTP \u2013 Physical signal slope control 8.5.1 1.CTC_5.1 \u2013 Duty cycle measurement 1 <\/td>\n<\/tr>\n | ||||||
85<\/td>\n | 8.5.2 1.CTC_5.2 \u2013 Duty cycle measurement 2 <\/td>\n<\/tr>\n | ||||||
87<\/td>\n | 8.5.3 1.CTC_5.3 \u2013 Duty cycle measurement 3 <\/td>\n<\/tr>\n | ||||||
88<\/td>\n | 8.5.4 1.CTC_5.4 \u2013 Propagation delay of the receiver test <\/td>\n<\/tr>\n | ||||||
90<\/td>\n | 8.5.5 1.CTC_5.5 \u2013 Propagation delay of the transmitter test <\/td>\n<\/tr>\n | ||||||
92<\/td>\n | 8.5.6 1.CTC_5.6 \u2013 Propagation delay of the transmitter test 2 <\/td>\n<\/tr>\n | ||||||
94<\/td>\n | 8.5.7 1.CTC_5.7 \u2013 Loop back time test <\/td>\n<\/tr>\n | ||||||
95<\/td>\n | 8.6 CTP \u2013 GND\/VBAT shift test 8.6.1 GND\/VBAT shift test set-up <\/td>\n<\/tr>\n | ||||||
96<\/td>\n | 8.6.2 1.CTC_6.1 \u2013 GND shift test <\/td>\n<\/tr>\n | ||||||
97<\/td>\n | 8.6.3 1.CTC_6.2 \u2013 VBAT shift test <\/td>\n<\/tr>\n | ||||||
98<\/td>\n | 8.7 CTP \u2013 Loss of power supply 8.7.1 Loss of battery and Loss of GND test set-up <\/td>\n<\/tr>\n | ||||||
99<\/td>\n | 8.7.2 1.CTC_7.1 \u2013 Loss of battery test (VBAT) <\/td>\n<\/tr>\n | ||||||
100<\/td>\n | 8.7.3 1.CTC_7.2 \u2013 Loss of GND test <\/td>\n<\/tr>\n | ||||||
101<\/td>\n | 8.8 CTP \u2013 Internal static capacity 8.8.1 Internal static capacity test set-up <\/td>\n<\/tr>\n | ||||||
102<\/td>\n | 8.8.2 1.CTC_8.1 Internal static capacity <\/td>\n<\/tr>\n | ||||||
104<\/td>\n | 8.9 CTP \u2013 Internal resistance measurement during operation 8.9.1 Internal resistor measurement test set-up <\/td>\n<\/tr>\n | ||||||
105<\/td>\n | 8.9.2 1.CTC_9.1\u2013 Internal resistor measurement 1 <\/td>\n<\/tr>\n | ||||||
106<\/td>\n | 8.9.3 1.CTC_9.2\u2013 Internal resistor measurement 2 <\/td>\n<\/tr>\n | ||||||
107<\/td>\n | 9 Physical layer conformance test plan (PS \u2013PMA non-separate type) 9.1 CTP \u2013 Operational conditions and calibration 9.1.1 1.CTC_10.1 \u2013 Clock transmission <\/td>\n<\/tr>\n | ||||||
109<\/td>\n | 9.1.2 1.CTC_10.2 \u2013 Detection of clock existence <\/td>\n<\/tr>\n | ||||||
110<\/td>\n | 9.1.3 1.CTC_10.3 \u2013 Arbitration function (stop transmission by arbitration) <\/td>\n<\/tr>\n | ||||||
111<\/td>\n | 9.1.4 1.CTC_10.4 \u2013 Operating voltage range <\/td>\n<\/tr>\n | ||||||
112<\/td>\n | 9.2 CTP \u2013 Wake-up pulse 9.2.1 General 9.2.2 1.CTC_11.1 \u2013 Wake-up pulse reception, IUT as master node <\/td>\n<\/tr>\n | ||||||
113<\/td>\n | 9.2.3 1.CTC_11.2 \u2013 Wake-up by clock detection <\/td>\n<\/tr>\n | ||||||
114<\/td>\n | 9.2.4 1.CTC_11.3 \u2013 Wake-up pulse transmission <\/td>\n<\/tr>\n | ||||||
115<\/td>\n | 9.3 CTP \u2013 Voltage and duty cycle thresholds 9.3.1 General 9.3.2 1.CTC_12.1 \u2013 Voltage threshold test 1 <\/td>\n<\/tr>\n | ||||||
117<\/td>\n | 9.3.3 1.CTC_12.2 \u2013 Voltage threshold test 2 <\/td>\n<\/tr>\n | ||||||
118<\/td>\n | 9.3.4 1.CTC_12.3 \u2013 Duty cycle threshold test 1 <\/td>\n<\/tr>\n | ||||||
121<\/td>\n | 9.3.5 1.CTC_12.4 \u2013 Duty cycle threshold test 2 <\/td>\n<\/tr>\n | ||||||
122<\/td>\n | 9.4 CTP \u2013 Network state current characteristics 9.4.1 1.CTC_13.1 \u2013 Drive current test <\/td>\n<\/tr>\n | ||||||
124<\/td>\n | 9.4.2 1.CTC_13.2 \u2013 Input leakage test <\/td>\n<\/tr>\n | ||||||
125<\/td>\n | 9.4.3 1.CTC_13.3 \u2013 Reverse leakage current test <\/td>\n<\/tr>\n | ||||||
126<\/td>\n | 9.5 CTP \u2013 Physical signal slope control 9.5.1 1.CTC_14.1 \u2013 Duty cycle measurement 1 <\/td>\n<\/tr>\n | ||||||
128<\/td>\n | 9.5.2 1.CTC_14.2 \u2013 Duty cycle measurement 2 <\/td>\n<\/tr>\n | ||||||
130<\/td>\n | 9.6 CTP \u2013 GND\/VBAT shift test 9.6.1 GND\/VBAT shift test set-up <\/td>\n<\/tr>\n | ||||||
131<\/td>\n | 9.6.2 1.CTC_15.1 \u2013 GND shift test <\/td>\n<\/tr>\n | ||||||
132<\/td>\n | 9.6.3 1.CTC_15.2 \u2013 VBAT shift test <\/td>\n<\/tr>\n | ||||||
133<\/td>\n | 9.7 CTP \u2013 Loss of power supply 9.7.1 General 9.7.2 Loss of battery (VBAT) and GND test set-up <\/td>\n<\/tr>\n | ||||||
134<\/td>\n | 9.7.3 1.CTC_16.1 \u2013 Loss of battery test (VBAT) <\/td>\n<\/tr>\n | ||||||
135<\/td>\n | 9.7.4 1.CTC_16.2 \u2013 Loss of GND test <\/td>\n<\/tr>\n | ||||||
136<\/td>\n | 9.8 CTP \u2013 Internal static capacity 9.8.1 Internal static capacity test set-up <\/td>\n<\/tr>\n | ||||||
137<\/td>\n | 9.8.2 1.CTC_17.1 Internal static capacity <\/td>\n<\/tr>\n | ||||||
139<\/td>\n | 9.9 CTP \u2013 Internal resistance measurement during operation 9.9.1 Internal resistor measurement test set-up <\/td>\n<\/tr>\n | ||||||
140<\/td>\n | 9.9.2 1.CTC_18.1\u2013 Internal resistor measurement 1 <\/td>\n<\/tr>\n | ||||||
141<\/td>\n | 9.9.3 1.CTC_18.2\u2013 Internal resistor measurement 2 <\/td>\n<\/tr>\n | ||||||
143<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Road vehicles. Clock extension peripheral interface (CXPI) – Data link and physical layer conformance test plan<\/b><\/p>\n |