BS EN IEC 60749-26:2018 – TC:2020 Edition
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Tracked Changes. Semiconductor devices. Mechanical and climatic test methods – Electrostatic discharge (ESD) sensitivity testing. Human body model (HBM)
| Published By | Publication Date | Number of Pages |
| BSI | 2020 | 124 |
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 70 | National foreword |
| 73 | English CONTENTS |
| 76 | FOREWORD |
| 78 | 1 Scope 2 Normative references 3 Terms and definitions |
| 81 | 4 Apparatus and required equipment 4.1 Waveform verification equipment |
| 82 | 4.2 Oscilloscope 4.3 Additional requirements for digital oscilloscopes 4.4 Current transducer (inductive current probe) 4.5 Evaluation loads |
| 83 | 4.6 Human body model simulator 4.7 HBM test equipment parasitic properties 5 Stress test equipment qualification and routine verification 5.1 Overview of required HBM tester evaluations Figures Figure 1 – Simplified HBM simulator circuit with loads |
| 84 | 5.2 Measurement procedures 5.2.1 Reference pin pair determination 5.2.2 Waveform capture with current probe |
| 85 | 5.2.3 Determination of waveform parameters |
| 86 | Figure 2 – Current waveform through shorting wires |
| 87 | Figure 3 – Current waveform through a 500 Ω resistor |
| 88 | 5.2.4 High voltage discharge path test 5.3 HBM tester qualification 5.3.1 HBM ESD tester qualification requirements 5.3.2 HBM tester qualification procedure Figure 4 – Peak current short circuit ringing waveform |
| 89 | 5.4 Test fixture board qualification for socketed testers |
| 90 | 5.5 Routine waveform check requirements 5.5.1 Standard routine waveform check description 5.5.2 Waveform check frequency Tables Table 1 – Waveform specification |
| 91 | 5.5.3 Alternate routine waveform capture procedure 5.6 High voltage discharge path check 5.6.1 Relay testers 5.6.2 Non-relay testers 5.7 Tester waveform records 5.7.1 Tester and test fixture board qualification records 5.7.2 Periodic waveform check records |
| 92 | 5.8 Safety 5.8.1 Initial set-up 5.8.2 Training 5.8.3 Personnel safety 6 Classification procedure 6.1 Devices for classification 6.2 Parametric and functional testing 6.3 Device stressing |
| 93 | 6.4 Pin categorization 6.4.1 General 6.4.2 No connect pins |
| 94 | 6.4.3 Supply pins 6.4.4 Non-supply pins |
| 95 | 6.5 Pin groupings 6.5.1 Supply pin groups 6.5.2 Shorted non-supply pin groups 6.6 Pin stress combinations 6.6.1 Pin stress combination categorization |
| 96 | Table 2 – Preferred pin combinations sets |
| 97 | 6.6.2 Non-supply and supply to supply combinations (1, 2, … N) Table 3 – Alternative pin combinations sets |
| 98 | 6.6.3 Non-supply to non-supply combinations |
| 99 | 6.7 HBM stressing with a low-parasitic simulator 6.7.1 Low-parasitic HBM simulator 6.7.2 Requirements for low parasitics 6.8 Testing after stressing 7 Failure criteria 8 Component classification |
| 100 | Table 4 – HBM ESD component classification levels |
| 101 | Annex A (informative)HBM test method flow chart Figure A.1 – HBM test method flow chart (1 of 3) |
| 104 | Annex B (informative)HBM test equipment parasitic properties B.1 Optional trailing pulse detection equipment / apparatus Figure B.1 – Diagram of trailing pulse measurement setup |
| 105 | B.2 Optional pre-pulse voltage rise test equipment Figure B.2 – Positive stress at 4 000 V Figure B.3 – Negative stress at 4 000 V |
| 106 | Figure B.4 – Illustration of measuring voltage before HBM pulsewith a Zener diode or a device Figure B.5 – Example of voltage rise before the HBM current pulseacross a 9,4 V Zener diode |
| 107 | B.3 Open-relay tester capacitance parasitics B.4 Test to determine if an HBM simulator is a low-parasitic simulator |
| 108 | Figure B.6 – Diagram of a 10-pin shorting test device showing current probe |
| 109 | Annex C (informative)Example of testing a product using Table 2, Table 3,or Table 2 with a two-pin HBM tester C.1 General Figure C.1 – Example to demonstrate the idea of the partitioned test |
| 110 | C.2 Procedure A (following Table 2): |
| 111 | C.3 Alternative procedure B (following Table 3): Table C.1 – Product testing in accordance with Table 2 |
| 112 | C.4 Alternative procedure C (following Table 2): Table C.2 – Product testing in accordance with Table 3 |
| 113 | Table C.3 – Alternative product testing in accordance with Table 2 |
| 114 | Annex D (informative)Examples of coupled non-supply pin pairs |
| 115 | Annex E (normative)Cloned non-supply (I/O) pin sampling test method E.1 Purpose and overview E.2 Pin sampling overview and statistical details |
| 116 | E.3 IC product selections Figure E.1 – SPL, V1, VM, and z with the Bell shapedistribution pin failure curve |
| 117 | E.4 Randomly selecting and testing cloned I/O pins E.5 Determining if sampling can be used with the supplied Excel spreadsheet E.5.1 Using the supplied Excel spreadsheet E.5.2 Without using the Excel spreadsheet E.6 HBM testing with a sample of cloned I/O pins |
| 118 | E.7 Examples of testing with sampled cloned I/Os |
| 120 | Figure E.2 – I/O sampling test method flow chart |
| 121 | Bibliography |
